Integrated circuit devices such as transistors are formed on semiconductor wafers. The devices are interconnected through metal lines and vias to form functional circuits, wherein the metal lines and vias are formed in back-end-of-line processes. To reduce the parasitic capacitance of the metal lines and vias, the metal lines and vias are formed in low-k dielectric layers.
In the formation of the metal lines and vias in a low-k dielectric layer, the low-k dielectric layer is first etched to form trenches and via openings. The etching of the low-k dielectric layer may involve forming a patterned hard mask over the low-k dielectric material, and using the patterned hard mask as an etching mask to form trenches. Via openings are also formed to substantially aligned to the trenches. The trenches and the via openings are then filled with a metallic material, which may include copper. A Chemical Mechanical Polish (CMP) is then performed to remove excess portions of the metallic material over the low-k dielectric layer. The remaining portions of the metallic material are metal lines and vias.
Conventional vias may suffer from distortion, particularly when the width of the metal lines and vias are very small. For example, the upper portions of the vias that are slightly lower than where vias join the overlying metal lines may suffer from kinks, which are portions that are narrower than both overlying and underlying portions of the respective vias.